1. Field of the Invention
The present invention relates to a clock generation circuit mounted on an image display device such as a display monitor or a television receiver.
2. Description of the Background Art
In a CRT (cathode ray tube), usually, there is a distortion in an image, depending on the overall shape of a Braun tube (cathode ray tube). Then, the distortion of the image is corrected by generating a distortion correction waveform. Further, because of variation in characteristics of parts, a horizontal position adjustment of screen is performed for each CRT in accordance with the characteristics of CRTs. The image distortion correction and the horizontal position adjustment of screen have been performed by using an analog circuit, but a desired operation with high accuracy cannot be necessarily obtained. A method to solve this situation is an image distortion correction and a horizontal position adjustment of screen using a digital signal.
FIG. 6 is a block diagram showing an overall constitution of a clock generation circuit in the background art which is proposed to perform the horizontal position adjustment and the image distortion correction using a digital signal. The clock generation circuit of FIG. 6 comprises two PLL circuits for generating clocks locked with received reference signals. This clock generation circuit is disclosed in, e.g., Japanese Patent Application Laid Open Gazette No. 2000-172213.
In FIG. 6, a first PLL circuit is constituted of a first phase comparator 1P (hereinafter, referred to as PC 1P), a first low-pass filter 2P (hereinafter, referred to as LPF 2P), a first voltage controlled oscillator 3P (hereinafter, referred to as VCO 3P) and a first (1/N) variable divider 4P (hereinafter, referred to as (1/N) divider 4P).
On the other hand, a second PLL circuit is constituted of a second phase comparator 7P (hereinafter, referred to as PC 7P), a second low-pass filter 8P (hereinafter, referred to as LPF 8P), a second voltage controlled oscillator 9P (hereinafter, referred to as VCO 9P), a second (1/N) variable divider 10P (hereinafter, referred to as (1/N) divider 10P), a horizontal drive pulse generation unit 11P and a deflection yoke 12P which a CRT 13P has.
Further, a digital delay unit 6P plays an important part in the above-discussed horizontal position adjustment of screen and the image distortion correction.
Next, an operation of the clock generation circuit having the above constitution will be discussed.
First, the PC 1P receives a horizontal synchronizing signal VHSYNC as a reference signal and compares the phases of the horizontal synchronizing signal VHSYNC and the other input signal VFP. The LPF 2P on the next stage smoothes an output signal from the PC 1P to generate a control voltage and outputs the control voltage to a control voltage receiving terminal of the VCO 3P. In accordance with the control voltage, the VCO 3P outputs a first clock signal CLK1P (hereinafter, referred to as clock CLK1P). The (1/N) divider 4P divides the frequency of the clock CLK1P into (1/N) (N is any positive integer) and transmits the output signal to the PC 1P as a feedback signal VFP. As a result, the phase of the feedback signal VFP is compared with the phase of the horizontal synchronizing signal VHSYNC by the PC 1P. Thus, the first PLL circuit works with the horizontal synchronizing signal VHSYNC used as the reference signal.
Next, the clock CLK1P and a first reset signal VRS1P (hereinafter, referred to as reset signal VRS1P) which corresponds to the feedback signal VFP are transmitted from an output end of the first PLL circuit to an input end of the digital delay unit 6P. The digital delay unit 6P starts a count operation of the clock CLK1P in response to the input timing of the reset signal VRS1P and outputs a horizontal delay reference signal VHDR which is delayed in phase from the reset signal VRS1P at the timing of coincidence between the count value and a digital value (any one of a digital value for horizontal position adjustment, a digital value for PIN balance correction and a digital value for KEY balance correction) which is set in the digital delay unit 6P before the reset signal VRS1P is inputted.
The horizontal delay reference signal VHDR is inputted to one input end of the PC 7P as a reference signal of the second PLL circuit. The PC 7P compares the phases of the horizontal delay reference signal VHDR and a signal VFBP received by the other input end and an output signal giving the phase difference is smoothed by the LPF 8P to become a control voltage of the VCO 9P. The VCO 9P performs an oscillation operation in accordance with the control voltage to output a second clock signal CLK2P (hereinafter, referred to as clock CLK2P). The (1/N) divider 10P divides the frequency of the clock CLK2P into 1/N (N is any positive integer) and transmits an output signal to the horizontal drive pulse generation unit 11P as a second reset signal VRS2P (hereinafter, referred to as reset signal VRS2P). The horizontal drive pulse generation unit 11P generates a horizontal drive pulse VHDP on the basis of the clock CLK2P and the reset signal VRS2P, to drive the deflection yoke 12P. With this driving operation, in a horizontal output circuit (not shown) which the deflection yoke 12P has, a flyback pulse of high energy is generated in a deflection coil (not shown) connected to a primary high-voltage winding of a flyback transformer (not shown) after a predetermined delay time passes from the input timing of the horizontal drive pulse VHDP. A step-down transformer circuit (not shown) having an input end connected to the one end of the deflection coil of the deflection yoke 12P lowers the voltage of the flyback pulse and outputs the voltage-lowered flyback pulse VFBP (hereinafter, referred to simply as flyback pulse VFBP) to the PC 7P. As a result, the PC 7P compares the phases of the horizontal delay reference signal VHDR and the flyback pulse VFBP. Thus, the second PLL circuit works to generate the horizontal drive pulse VHDP with the horizontal delay reference signal VHDR used as the reference signal.
FIGS. 7A to 7E are timing charts of the signals at the time when the clock generation circuit of FIG. 6 is brought into a steady state by the locking operation of the first and second PLL circuits.
Specifically, FIG. 7A shows the horizontal synchronizing signal VHSYNC which corresponds to the reference signal of the first PLL circuit, and the horizontal synchronizing signal VHSYNC is inputted to the PC 1P. FIG. 7B shows the feedback signal VFP or the reset signal VRS1P of the first PLL circuit, and the feedback signal VFP is inputted to the PC 1P and outputted to the digital delay unit 6P at the same time. The first PLL circuit in the steady state keeps a condition where the phase difference between the horizontal synchronizing signal VHSYNC of FIG. 7A and the feedback signal VFP of FIG. 7B is a time AD.
On the other hand, FIG. 7C shows the horizontal delay reference signal VHDR which corresponds to the reference signal of the second PLL circuit, and the horizontal delay reference signal VHDR is generated by the digital delay unit 6P. A time period from an input timing (rise timing) of the reset signal VRS1P of FIG. 7B to the output timing (fall timing) of the horizontal delay reference signal VHDR of FIG. 7C is a delay time BD produced by the digital delay unit 6P. Specifically, the digital delay unit 6P generates the horizontal delay reference signal VHDR having a predetermined delay time BD in accordance with any one of the digital value for horizontal position adjustment, the digital value for PIN balance correction and the digital value for KEY balance correction which is set in the digital delay unit 6P, and the image display device performs the horizontal position adjustment of screen and/or the image distortion correction by using the delay time BD.
FIG. 7D shows the flyback pulse VFBP, and the flyback pulse VFBP is inputted to the PC 7P along with the horizontal delay reference signal VHDR of FIG. 7C. In a locked state, the second PLL circuit keeps a condition where the phase difference between the horizontal delay reference signal VHDR and the flyback pulse VFBP is a predetermined time CD shown in FIG. 7D.
FIG. 7E shows the horizontal drive pulse VHDP, and the horizontal drive pulse VHDP is a pulse whose duty ratio is almost 1:1 in one horizontal scanning period. As shown in FIG. 7E, there is a delay time DD between an edge (herein, rising edge) of the horizontal drive pulse VHDP and an edge (herein, rising edge) of the flyback pulse VFBP in the locked state.
The background-art clock generation circuit of FIG. 6 uses the output signal VHDR from the digital delay unit 6P which is driven on the basis of the clock CLK1P outputted from the first PLL circuit as the reference signal inputted to the PC 7P of the second PLL circuit. For this reason, in the second PLL circuit which operates while generating the clock CLK2P, the reference signal of the second PLL circuit always has some jitter.
Moreover, every time when the horizontal position adjustment, the PIN balance correction or the KEY balance correction is performed, the phase of the horizontal delay reference signal VHDR generated by the digital delay unit 6P largely varies.
Further, the flyback pulse VFBP serving as the feedback signal of the second PLL circuit is a signal which is likely to vary, depending on various factors including the type of used monitor, resolution and ambient temperature. In other words, the delay time DD in the locked state varies with the ambient temperature and the like.
Thus, since the phases of the two signals (the horizontal delay reference signal VHDR and the flyback pulse VFBP) inputted to the PC 7P of the second PLL circuit largely vary, the second PLL circuit has a large load, being likely to become unstable. Therefore, some jitter is generated in the clock CLK2P outputted from the VCO 9P of the second PLL circuit and as a result, the phase of the horizontal drive pulse VHDP varies and as a result, some jitter is disadvantageously likely to appear on the screen of the CRT 13P.
The present invention is directed to a clock generation circuit. According to a first aspect of the present invention, the clock generation circuit comprises: an input signal line comprising one end connected to a flyback pulse output terminal which an external deflection yoke has; and a phase locked loop circuit comprising an input terminal connected to the other end of the input signal line, and in the clock generation circuit of the first aspect, the phase locked loop circuit comprises a phase comparator comprising a first input terminal which corresponds to the input terminal and a second input terminal receiving a feedback signal; a low-pass filter comprising an input terminal connected to an output terminal of the phase comparator; a voltage controlled oscillator comprising a control voltage terminal connected to an output terminal of the low-pass filter; and a (1/N) divider (N is a positive integer) comprising an input terminal connected to an output terminal of the voltage controlled oscillator and an output terminal connected to the second input terminal of the phase comparator.
According to a second aspect of the present invention, the clock generation circuit of the first aspect further comprises: a delay circuit comprising a first input terminal connected to the other end of the input signal line and a second input terminal connected to the output terminal of the voltage controlled oscillator, the delay circuit detecting an edge of a flyback pulse and outputting a flyback delay signal which is delayed from the edge by a predetermined delay time, and in the clock generation circuit of the second aspect, the predetermined delay time corresponds to the amount of horizontal movement on a screen of a cathode ray tube comprising the deflection yoke.
According to a third aspect of the present invention, in the clock generation circuit of the second aspect, the phase locked loop circuit, the phase comparator, the low-pass filter, the voltage controlled oscillator and the (1/N) divider are defined as a first phase locked loop circuit, a first phase comparator, a first low-pass filter, a first voltage controlled oscillator and a first (1/N) divider, and the clock generation circuit of the third aspect further comprises a second phase locked loop circuit comprising a first input terminal receiving a horizontal synchronizing signal, a second input terminal connected to an output terminal of the delay circuit and an output terminal connected to a horizontal drive pulse receiving terminal which the deflection yoke has, and in the clock generation circuit of the third aspect, the second phase locked loop circuit comprises a second phase comparator comprising the first input terminal and the second input terminal of the second phase locked loop circuit; a second low-pass filter comprising an input terminal connected to an output terminal of the second phase comparator; a second voltage controlled oscillator comprising a control voltage terminal connected to an output terminal of the second low-pass filter; a second (1/N) divider comprising an input terminal connected to an output terminal of the second voltage controlled oscillator; and a horizontal drive pulse generation unit comprising a first input terminal connected to an output terminal of the second (1/N) divider and a second input terminal connected to the output terminal of the second voltage controlled oscillator, the horizontal drive pulse generation unit generating a horizontal drive pulse and outputting the horizontal drive pulse from the output terminal of the second phase locked loop circuit.
According to a fourth aspect of the present invention, in the clock generation circuit of any one of the first to third aspects, the input signal line comprises a step-down transformer circuit.
The present invention is also directed to an image display device. According to a fifth aspect of the present invention, the image display device comprises: the clock generation circuit of any one of the first to fourth aspects; and a cathode ray tube, and in the image display device of the fifth aspect, the cathode ray tube comprises a deflection yoke comprising a flyback pulse output terminal connected to the one end of the input signal line and a horizontal drive pulse receiving terminal connected to the output terminal of the second phase locked loop circuit.
The present invention is directed to a clock generation circuit again. According to a sixth aspect of the present invention, the clock generation circuit comprises: input means for transmitting a flyback pulse supplied from an external deflection yoke; and first phase locked loop means for receiving the flyback pulse from the input means as a first reference signal, and for generating a first clock signal in synchronization with the flyback pulse.
According to a seventh aspect of the present invention, the clock generation circuit of the sixth aspect further comprises delay means for receiving the flyback pulse and the first clock signal from the input means and the first phase locked loop means, respectively, and for detecting an edge of the flyback pulse and generating a flyback delay signal which is delayed from the edge by a predetermined delay time, and in the clock generation circuit of the seventh aspect, the predetermined delay time corresponds to the amount of horizontal movement on a screen of a cathode ray tube comprising the deflection yoke.
According to an eighth aspect of the present invention, the clock generation circuit of the seventh aspect further comprises second phase locked loop means for receiving a horizontal synchronizing signal and the flyback delay signal as a second reference signal and a compared signal, respectively, and for generating a horizontal drive pulse, and in the clock generation circuit of the eighth aspect, the second phase locked loop means comprises phase comparator means for comparing a phase of the horizontal synchronizing signal and a phase of the flyback delay signal to generate a phase difference signal giving a phase difference between the horizontal synchronizing signal and the flyback delay signal; low-pass filter means for smoothing the phase difference signal to output a smoothed signal; voltage controlled oscillator means for receiving the smoothed signal as a control signal, and for performing an oscillation operation in accordance with the control signal to generate a second clock signal; (1/N) divider means for dividing a frequency of the second clock signal to generate a reset signal whose frequency is 1/N of the frequency of the second clock signal; and horizontal drive pulse generation means for generating the horizontal drive pulse for the deflection yoke on the basis of the second clock signal and the reset signal.
According to a ninth aspect of the present invention, in the clock generation circuit of the eighth aspect, the input signal means comprises step-down transformer means for lowering a voltage of a high-voltage flyback pulse outputted from the deflection yoke to generate the flyback pulse.
The present invention is directed to an image display device again. According to a tenth aspect of the present invention, the image display device comprises: the clock generation circuit of the ninth aspect; and a cathode ray tube, and in the image display device of the tenth aspect, the cathode ray tube comprises a deflection yoke comprising a flyback pulse output terminal connected to an input terminal of the step-down transformer means and a horizontal drive pulse receiving terminal connected to an output terminal of the horizontal drive pulse generation means.
The present invention has the above constitution, and therefore produces the following effects.
In the clock generation circuit of the first aspect of the present invention, since the PLL circuit receives the flyback pulse and the feedback signal which is obtained by dividing a clock outputted from the voltage controlled oscillator as the reference signal and the compared signal, respectively, to perform a locking operation, the PLL circuit absorbs more quickly a phase fluctuation of the flyback pulse caused by various factors such as ambient temperature and can therefore generate a stable clock.
In the clock generation circuit of the second aspect of the present invention, it is possible to generate the flyback delay signal having a predetermined delay signal needed for the horizontal position adjustment, the PIN balance correction or the KEY balance correction on the basis of the flyback pulse and the clock outputted from the PLL circuit.
In the clock generation circuit of the third aspect and the image display device of the fifth aspect of the present invention, since the first PLL circuit can quickly absorb the phase fluctuation of the flyback pulse to generate a stable clock and moreover the second PLL circuit receives the stable horizontal synchronizing signal with no jitter as its reference signal, the second PLL circuit can operate more stably. Thus, as the result of the above two factors, the present invention can exert effects of generating the stable horizontal drive pulse with no jitter and effectively preventing the jitter from appearing on the screen.
The clock generation circuit of the fourth aspect of the present invention can produce an effect of protecting the phase comparator from the high-voltage flyback pulse when the phase comparator having the input terminal connected to the other end of the input signal line can not directly receive the high-voltage flyback pulse in terms of its characteristics.
An object of the present invention is to provide a clock generation circuit capable of generating a stable horizontal drive pulse which causes no jitter on a screen and an image display device on which the clock generation circuit is mounted.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.